The present disclosure relates generally to semiconductor manufacturing. Specifically, the present disclosure relates to metallization of integrated circuit semiconductor devices. More specifically, the present disclosure relates to a semiconductor device having an improved high aspect ratio via and a method of fabricating the same.
The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the mainstream course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased. However, this mainstream evolution needs to follow the Moore's rule by a huge investment in facility establishment. Therefore, it has been a study topic that using current semiconductor technology develops more valuable ICs product. A complimentary metal oxide semiconductor (CMOS) microelectromechanical systems (MEMS) device happens to be a good candidate for that trend.
As is well understood in the art, semiconductor devices are typically formed using multiple layers of material, including conductive, semi-conductive, and insulative layers. To provide electrical conductivity between layers in a semiconductor device, a hole or via may be formed through certain layers. The via is then lined with a barrier layer, such as Ti, TiN, or Ti/TiN, and filled with an electrically conductive material, such as a metal, to provide electrical conductivity between the layers.
CMOS MEMS devices are very small electro-mechanical systems incorporated into CMOS semiconductor IC circuits. MEMS devices are a type of semiconductor device that use vias to provide electrical conductivity between layers of the device. One example of a MEMS device is a micro-inertial sensor. With an increase of via aspect ratio (e.g., via depth/size) due to ever shrinking geometries of semiconductor devices, it becomes more and more difficult to provide good step coverage of the barrier layer in the via.
If the barrier layer film coverage is not thick enough, the reactant gas (e.g., WF6) of a following wet-chemical vapor deposition (CVD) process will attack the via sidewall silicon and create defect problems for the via, such as voids or other open circuit issues. One reason for such problems is that low resistivity silicon wafers are conventionally used in MEMS device applications. Silicon allows for a native oxide to be easily formed in the via during the via hole etching process, especially along the via sidewalls. If the sidewall oxide can not be fully removed, it can block electrical signals from passing to and from the MEMS sensor, and thus rendering the device defective. Therefore, to solve one or more of the above mentioned issues, what is needed is an improved semiconductor device having an improved high aspect ratio via, and a method of fabrication for the same.